#ifndef _qspicfprv_h_
#define _qspicfprv_h_ 1
/**HEADER********************************************************************
* 
* Copyright (c) 2010 Avnet Japan Co.,Ltd (NIKE Borad Project.)
* All Rights Reserved
*
*************************************************************************** 
*
* $FileName: P5Q_spi_mcf52xx_prv.h$
* $Version : 0.1.0.0$
* $Date    : Jan-29-2010$
*
* Comments:
*
*
*END************************************************************************/

extern uchar __IPSBAR[];

/*********************************************************************
*
* Queued Serial Peripheral Interface (QSPI) Module
*
*********************************************************************/

/*
** QSPI addresses
*/
#define QSPI_ADDRESS        (void *)(&__IPSBAR[0x0340])

/* 
** Max. frequency of QSPI clock is 1/4 of internal 
** bus clock frequency 
*/
#ifdef PSP_MCF5282
#if MCF5275_PROCESSOR
#define MAX_QSPI_CLK        (BSP_SYSTEM_CLOCK/2)/4
#else
#define MAX_QSPI_CLK        BSP_SYSTEM_CLOCK/4
#endif
#endif

/* 
** Register read/write
*/
#define QSPI_QMR            (*(volatile uint_16*)(void*)(&__IPSBAR[0x0340]))
#define QSPI_QDLYR          (*(volatile uint_16*)(void*)(&__IPSBAR[0x0344]))
#define QSPI_QWR            (*(volatile uint_16*)(void*)(&__IPSBAR[0x0348]))
#define QSPI_QIR            (*(volatile uint_16*)(void*)(&__IPSBAR[0x034C]))
#define QSPI_QAR            (*(volatile uint_16*)(void*)(&__IPSBAR[0x0350]))
#define QSPI_QDR            (*(volatile uint_16*)(void*)(&__IPSBAR[0x0354]))
#define QSPI_QCR		    (*(volatile uint_16*)(void*)(&__IPSBAR[0x0354]))

/*
**  Bit definitions and macros for QSPI Mode Register
*/
#define QSPI_QMR_MSTR       0x8000
#define QSPI_QMR_DOHIE      0x4000
#define QSPI_QMR_BITS(x)    (((x)&0x000F)<<10)
#define QSPI_QMR_CPOL       0x0200
#define QSPI_QMR_CPHA       0x0100
#define QSPI_QMR_BAUD(x)    ((x)&0x00FF)
		
/*
** Bit definitions and macros for QSPI Delay Register
*/
#define QSPI_QDLYR_SPE      0x8000
#define QSPI_QDLYR_QCD(x)   (((x)&0x007F)<<8)
#define QSPI_QDLYR_DTL(x)   ((x)&0x00FF)

/*
** Bit definitions and macros for QSPI Wrap register
*/
#define QSPI_QWR_HALT       0x8000
#define QSPI_QWR_WREN       0x4000
#define QSPI_QWR_WRTO       0x2000
#define QSPI_QWR_CSIV       0x1000
#define QSPI_QWR_ENDQP(x)   (((x)&0x000F)<<8)
#define QSPI_QWR_NEWQP(x)   ((x)&0x000F)

/*
** Bit definitions and macros for QSPI Interrupt Register
*/
#define QSPI_QIR_WCEFB      0x8000
#define QSPI_QIR_ABRTB      0x4000
#define QSPI_QIR_ABRTL      0x1000
#define QSPI_QIR_WCEFE      0x0800
#define QSPI_QIR_ABRTE      0x0400
#define QSPI_QIR_SPIFE      0x0100
#define QSPI_QIR_WCEF       0x0008
#define QSPI_QIR_ABRT       0x0004
#define QSPI_QIR_SPIF       0x0001
							
/*
** Bit definitions and macros for QSPI Address Register
*/
#define QSPI_QAR_ADDR(x)    (((x)&0x003F))

#define QSPI_QDR_COMMAND(x) (((x)&0xFF00))

/*
** Bit definitions and macros for QSPI Data Register
*/
#define QSPI_QDR_DATA(x)    ((x)&0xFFFF)
						     
/*
** Bit definitions and macros for QSPI Command RAM Register QCR0-QCR15
*/
#define QSPI_QCR_DATA(x)    (((x)&0x00FF)<<8)
#define QSPI_QCR_CONT       0x8000
#define QSPI_QCR_BITSE      0x4000
#define QSPI_QCR_DT         0x2000
#define QSPI_QCR_DSCK       0x1000
#define QSPI_QCR_CS(x)      (((x)&0x000F)<<8)

/*
** QSPI error codes
*/
#define QSPI_OK             (0x00)
#define QSPI_UNDEF_ERROR             (QSPI_ERROR_BASE | 0x01)
#define QSPI_INVALID_ADDRESS         (QSPI_ERROR_BASE | 0x02)
#define QSPI_TRANSFER_MODE_INVALID   (QSPI_ERROR_BASE | 0x03)
#define QSPI_DEINIT_FAILED           (QSPI_ERROR_BASE | 0x04)
#define QSPI_BAUDRATE_INVALID        (QSPI_ERROR_BASE | 0x05)
#define QSPI_BRG_FAILD               (QSPI_ERROR_BASE | 0x06)
#define QSPI_CHIPSELECT_INVALID      (QSPI_ERROR_BASE | 0x07)
#define QSPI_TX_NO_DATA              (QSPI_ERROR_BASE | 0x08)
#define QSPI_TIMED_OUT               (QSPI_ERROR_BASE | 0x09)
					   
/* Timeout used by QSPI device driver (number of milliseconds) */
#define QSPI_TIMEOUT        10

/*--------------------------------------------------------------------------*/
/*
**                    DATATYPE DECLARATIONS
*/

/*
** MCF52XX_P5Q_SPI_INFO_STRUCT
** Run time state information for each serial channel
*/
typedef struct mcf52xx_P5Q_spi_info_struct
{
   /* The current init values for this port */
   MCF52XX_P5Q_SPI_INIT_STRUCT          INIT;
   
   /* Interrupt code required if interrupt driven */
   uint_32                           INT_BITS;

   /* The previous interrupt handler and data */
   void       (_CODE_PTR_ OLD_ISR)(pointer);
   void       (_CODE_PTR_ OLD_ISR_EXCEPTION_HANDLER)(uint_32, uint_32, pointer, pointer);
   pointer                           OLD_ISR_DATA;

   /* Total number of bytes to read */
   uint_32                           TOTAL_SIZE;

   /* Number of bytes to read */
   uint_32                           BYTE_COUNT;

   /* Pointer to the buffer to use for Tx/Rx data */
   uchar_ptr                         BUFFER;

   /* Rx index */
   uint_32                           RX_INDEX;

   /* Current Rx buffer length */
   uint_32                           RX_BUF_LEN;

   /* Pointer to the buffer to use for current Tx data */
   uchar_ptr                         TX_BUF;

   /* Tx index */
   uint_32                           TX_INDEX;

   /* Current Tx buffer length */
   uint_32                           TX_BUF_LEN;

   /* Statistical information */
   uint_32                           INTERRUPTS;
   uint_32                           RX_PACKETS;
   uint_32                           TX_PACKETS;
   uint_32                           TX_ABORT;

} MCF52XX_P5Q_SPI_INFO_STRUCT, _PTR_ MCF52XX_P5Q_SPI_INFO_STRUCT_PTR;

/*-----------------------------------------------------------------------*/
/*                      FUNCTION PROTOTYPES                              */
/*-----------------------------------------------------------------------*/
#ifdef __cplusplus
extern "C" {
#endif

extern void _mcf_qspi_int_isr(pointer);

#ifdef __cplusplus
}
#endif

#endif

/* EOF */