#ifndef _P5Q_SPI_h
#define _P5Q_SPI_h 1
/**HEADER********************************************************************
* 
* Copyright (c) 2010 Avnet Japan Co.,Ltd (NIKE Borad Project.)
* All Rights Reserved
*
*************************************************************************** 
*
* $FileName: P5Q_spi.h$
* $Version : 0.1.0.0$
* $Date    : Jan-29-2010$
*
* Comments:
*
*
*END************************************************************************/

#include "ioctl.h"

/*
** QSPI Transfer size 
*/
#define QSPI_QMR_8_BITS     0x08
#define QSPI_QMR_9_BITS     0x09
#define QSPI_QMR_10_BITS    0x0A
#define QSPI_QMR_11_BITS    0x0B
#define QSPI_QMR_12_BITS    0x0C
#define QSPI_QMR_13_BITS    0x0D
#define QSPI_QMR_14_BITS    0x0E
#define QSPI_QMR_15_BITS    0x0F
#define QSPI_QMR_16_BITS    0x00

/* At this time only min. and max supported */
#define QSPI_MAX_TRANSFER_SIZE  QSPI_QMR_16_BITS
#define QSPI_MIN_TRANSFER_SIZE  QSPI_QMR_8_BITS

/* QSPI buffer size, in bytes */
#define DEFAULT_QSPI_RX_BUFFER_SIZE 32
#define DEFAULT_QSPI_TX_BUFFER_SIZE 32

/* 
** QSPI IOCTL Calls
*/

/* chip select states */
#define QSPI_CHIP_SELECT_SET_1  1
#define QSPI_CHIP_SELECT_SET_0  0

#define QSPI_TRANSFER_8_BITS   8
#define QSPI_TRANSFER_16_BITS  16

/*
** QSPI R/W operations
*/
#define QSPI_WRITE_OP 0x00
#define QSPI_READ_OP  0x01

/* 
** QSPI device modes of operation 
*/
#define QSPI_DEVICE_SLAVE_MODE            (0x021A) // Not supported
#define QSPI_DEVICE_MASTER_MODE           (0x021B) 

/*
** QSPI Tx RAM
*/
#define QSPI_QTR0           0x00
#define QSPI_QTR1           0x01
#define QSPI_QTR2           0x02
#define QSPI_QTR3           0x03
#define QSPI_QTR4           0x04
#define QSPI_QTR5           0x05
#define QSPI_QTR6           0x06
#define QSPI_QTR7           0x07
#define QSPI_QTR8           0x08
#define QSPI_QTR9           0x09
#define QSPI_QTR10          0x0A
#define QSPI_QTR11          0x0B
#define QSPI_QTR12          0x0C
#define QSPI_QTR13          0x0D
#define QSPI_QTR14          0x0E
#define QSPI_QTR15          0x0F

/*
** QSPI Rx RAM
*/
#define QSPI_QRR0           0x10
#define QSPI_QRR1           0x11
#define QSPI_QRR2           0x12
#define QSPI_QRR3           0x13
#define QSPI_QRR4           0x14
#define QSPI_QRR5           0x15
#define QSPI_QRR6           0x16
#define QSPI_QRR7           0x17
#define QSPI_QRR8           0x18
#define QSPI_QRR9           0x19
#define QSPI_QRR10          0x1A
#define QSPI_QRR11          0x1B
#define QSPI_QRR12          0x1C
#define QSPI_QRR13          0x1D
#define QSPI_QRR14          0x1E
#define QSPI_QRR15          0x1F

/*
** QSPI Command RAM
*/
#define QSPI_QCR0           0x20
#define QSPI_QCR1           0x21
#define QSPI_QCR2           0x22
#define QSPI_QCR3           0x23
#define QSPI_QCR4           0x24
#define QSPI_QCR5           0x25
#define QSPI_QCR6           0x26
#define QSPI_QCR7           0x27
#define QSPI_QCR8           0x28
#define QSPI_QCR9           0x29
#define QSPI_QCR10          0x2A
#define QSPI_QCR11          0x2B
#define QSPI_QCR12          0x2C
#define QSPI_QCR13          0x2D
#define QSPI_QCR14          0x2E
#define QSPI_QCR15          0x2F

/*
** QSPI Chip Selects
*/
#define QSPI_CS0            0x0E
#define QSPI_CS1			0x0D
#define QSPI_CS2			0x0B
#define QSPI_CS3			0x07

/*
** QSPI Transfer modes
*/
#define QSPI_TRANSFER_MODE_1    1  // Active low; QSPI_CLK transitions middle of bit timing
#define QSPI_TRANSFER_MODE_2	2  // Active high; QSPI_CLK transitions middle of bit timing
#define QSPI_TRANSFER_MODE_3	3  // Active low; QSPI_CLK transitions begining of bit timing
#define QSPI_TRANSFER_MODE_4    4  // Active high; QSPI_CLK transitions begining of bit timing

/* 
** IOCTL calls specific to QSPI 
*/
#define IO_IOCTL_QSPI_CLEAR_RX_CHARS                   _IO(IO_TYPE_QSPI,0x11)
#define IO_IOCTL_QSPI_RETURN_IMMEDIATE                 _IO(IO_TYPE_QSPI,0x12)
#define IO_IOCTL_QSPI_GET_CURRENT_MODE                 _IO(IO_TYPE_QSPI,0x13)
#define IO_IOCTL_QSPI_DISABLE_DEVICE                   _IO(IO_TYPE_QSPI,0x14)
#define IO_IOCTL_QSPI_ENABLE_DEVICE                    _IO(IO_TYPE_QSPI,0x15)
#define IO_IOCTL_QSPI_GET_LAST_COMMAND_COMPLETE        _IO(IO_TYPE_QSPI,0x16)
#define IO_IOCTL_QSPI_CHIP_SELECT                      _IO(IO_TYPE_QSPI,0x17)
#define IO_IOCTL_QSPI_SET_TRANSFER_MODE                _IO(IO_TYPE_QSPI,0x18)
#define IO_IOCTL_QSPI_SET_CHIP_SELECT_STATE            _IO(IO_TYPE_QSPI,0x19)
#define IO_IOCTL_QSPI_SET_TRANSFER_SIZE                _IO(IO_TYPE_QSPI,0x1A)


#define IO_IOCTL_QSPI_SET_ADDR                         _IO(IO_TYPE_QSPI,0x1B)
#define IO_IOCTL_QSPI_GET_ADDR                         _IO(IO_TYPE_QSPI,0x1C)
#define IO_IOCTL_QSPI_SET_MEM                          _IO(IO_TYPE_QSPI,0x1D)
#define IO_IOCTL_QSPI_GET_MEM                          _IO(IO_TYPE_QSPI,0x1E)
#define IO_IOCTL_QSPI_SCTOR_ERASE                      _IO(IO_TYPE_QSPI,0x1F)

#define IO_IOCTL_QSPI_BLOCK_SET_MEM                    _IO(IO_TYPE_QSPI,0x20)
#define IO_IOCTL_QSPI_BLOCK_GET_MEM                    _IO(IO_TYPE_QSPI,0x21)
#define IO_IOCTL_QSPI_BLOCK_ERASE                      _IO(IO_TYPE_QSPI,0x22)


typedef struct
{
	uint_32	addr;
	uchar *data;
	uint_32	size;
}PCM_SPI_MAMORY_IO, *PPCM_SPI_MAMORY_IO;



/*--------------------------------------------------------------------------*/
/* 
**                        FUNCTION PROTOTYPES
*/

#ifdef __cplusplus
extern "C" {
#endif

extern _mqx_uint _io_P5Q_spi_install(
                   char_ptr,
                   _mqx_uint(_CODE_PTR_)(pointer, pointer _PTR_, char _PTR_),
                   _mqx_uint(_CODE_PTR_)(pointer, pointer),
                   _mqx_int(_CODE_PTR_)(pointer, char _PTR_, _mqx_int),
                   _mqx_int(_CODE_PTR_)(pointer, char _PTR_, _mqx_int),
                   _mqx_int(_CODE_PTR_)(pointer, _mqx_uint, _mqx_uint_ptr), pointer);


#ifdef __cplusplus
}
#endif

#endif

/* EOF */
